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Master Thesis in Virtual Prototyping and Verification
Reutlingen
Aktualität: 11.11.2024
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11.11.2024, Bosch-Gruppe
Reutlingen
Master Thesis in Virtual Prototyping and Verification
Aufgaben:
We develop and manufacture semiconductors, sensors, and control units for automotive applications. Complex Systems-on-Chip (SoC) often contain one or more on-chip processors that run software tasks. Virtual Prototypes can be used for efficient pre- and post-silicon software development enabling earlier and more flexible verification as well as software development. During your master thesis you will focus on achieving a flexible and configurable verification approach to speed-up verification of digital design representation at different levels of abstraction and to construct a scheme to classify the test cases within the scope. Quantitative and qualitative metrics will be used to demonstrate the effectiveness of the implemented verification approach. You will learn modern approaches to efficiently develop and integrate virtual prototypes. Furthermore, you will also get familiar with cross-verification of SoC designs in unified verification methodology.
Qualifikationen:
Education: Master studies in the field of Computer Science, Electrical Engineering, Electronics Engineering or comparable Experience and Knowledge: in object-oriented programming, digital hardware; knowledge of processor architectures, C++, SystemVerilog and UVM Personality and Working Practice : you excel at generating new ideas, asking questions, and actively collaborating with the team to efficiently achieve shared goals Languages: very good in written and spoken English
Standorte
Master Thesis in Virtual Prototyping and Verification
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