Ihre Aufgaben:
* Esponsible for defining and writing verification plans based on requirements documents
* Define verification strategy according to design specification documents
* Responsible for architecting and developing UVM- and software-based verification environments for RTL simulation
* Define and develop test cases within an appropriate verification framework
* Create stimulus and assertions, run simulations, and debug test cases on design models (RTL, Gate level, Emulation platform)
* Run regressions, collect, and analyze code/functional coverage
* Provide guidance and support to verification engineers
Ihre Qualifikationen:
* Proven experience in testbench design and development using UVM methodology for IP/Subsystem/SoCs
* Proven experience in verification sign-off at IP/Sub System/SoC level with test plan development, functional & code coverage analysis
* Proven experience in EDA tools from Cadence (Xcelium, Simvision, Verisium, vManager, Jasper) and / or Synopsys (VCS, Verdi)
* Understanding of software development for embedded CPUs, and experience in developing and debugging software
* Basic experience in execution of Gate Level Netlist simulation with back-annotated timing / Basic experience on writing System Verilog assertions / Basic understanding of Formal flow /methodologies
* Ability to question and identify weaknesses in specifications, tool environments, etc.
* Pro-active attituded engineer with proven experience in digital IP & SoC verification & good communication skills
* Fluency in English language.
* M.Sc. Degree in Electrical Engineering or Computer Science, with 5+ years of experience on IP/Sub-System/SoC Verification
Ihre Vorteile:
* Interesting tasks in a multinational environment
* A very renowned company