Your Tasks
* Methods and strategies for efficient functional and formal digital verification with UVM, including the emulation of digital System-on-Chip (SoC) with RISC-V and mixed-signal IP
* Expansion of collaboration with the Fraunhofer IIS for integrated digital systems
* Publication and presentation of research results
* Supervision of Bachelor's and Master's theses, as well as conducting teaching exercises, seminars, or computer labs
Your Profile
* Completed academic degree (Master's/Diploma) in digital circuit technology or a related field
* Good knowledge of SystemVerilog and/or VHDL as well as FPGAs
* Excellent English skills (minimum C2 level)
Benefits: We Have a Lot To Offer
* Regular promotion to the next level and increase in salary pursuant to the collective bargaining agreement for the public service of the German Länder (TV-L) or remuneration pursuant to the Bavarian Public Servants Remuneration Act (BayBesG) plus an additional annual bonus
* 30 days annual leave at five working days per week with additional free days on December 24 and 31
* Occupational pension scheme and asset accumulation savings scheme
* Excellent support during the academic qualification phase
* Systematic career development in collaboration with the Graduate Center
* Thorough onboarding process with a dedicated team
* Joint team activities
* Subsidized food and drinks in our student restaurants
* Place of work within comfortable walking distance of public transport
* Family-friendly environment with childcare options, also during school holidays
* Flexible working hours
* A wide range of training courses and opportunities for professional development
* Active health management
PaymentTV-L E 13