Physical Design Enginer - STA
European Tech Recruit are working closely with a leading semicon company, based in Dortmund, who are looking for a talented Physical Design Engineer with strong STA knowledge to join their team.
This role is also available onsite at the client's Lausanne (Switzerland), Copenhagen (Denmark) and Northampton (UK) sites.
Responsibilities as Physical Design Engineer :
* As a Physical Design Engineer, you will work closely with the Architecture and RTL team to ensure first-time-right high-volume silicon production.
* Timing Constraints development, timing constraints validation, sign-off Static Timing Analysis and support for full chip & block-level timing closure will be the primary focus and responsibility.
* Block and chip level STA with all aspects, reviewing and defining constraints with the design team, implementing SDC constraints to be used for block and chip (flat) STA, analyze violations and clean with help of frontend design and PD team.
* Participate in developing improvements to scripts/methodologies/flows.
* Interact closely with the design team to understand requirements and implement solutions for STA.
* Support IP and chip level integration.
Requirements:
* Good knowledge of RTL to GDS implementation flow (synthesis, P&R, LEC, STA).
* Self-motivated, with strong sense of ownership and responsibility. Good communicator and team player.
* Good scripting capabilities (shell, TCL, Python, make) and good understanding of data management (revision control system).
* Experience in gathering and defining SDC constraints, specifically on top-level incl. DFT. Requires great team-work, tenacity, stamina and eye-for-detail. Also requires excellent communication and people skills to pull information from team members.
* Flow development with focus on cross project reusability.
If this role is of any interest please apply directly on LinkedIn or send a copy of your CV to nh@eu-recruit.com.
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