An established Semiconductor company and University spin off in the data communication market with offices in Austria and Germany are looking for a Senior Mixed Signal Design Verification Engineer to join their Design team in Mannheim, Germany or Villach, Austria. In your role as a Senior Mixed Signal Design Verification Engineer you will own the pre-silicon functional verification of certain building blocks and have the following responsibilities:
* Create and execute test plan for the AMS design verification
* Design, implement and continuously improve the AMS test bench setup
* Extract modeling specifications from circuit design
* Create RNM Verilog models of analog circuits in close cooperation with the full-custom design team
* Develop and refine test cases and simulation models
* Setup and facilitate verification reviews
* Work closely and cross-functional across different groups to support a successful and on-time product release
As the successful Senior AMS Verification Engineer you are industry degree qualified and have at least 5 years of experience in the following, ideally in a UVM environment:
* Cadence design flow and EDA tools
* Script programming languages such as Python, TCL, Skill
* System Verilog Real Number Modelling
To learn more about this opportunity, please contact Molly at IC Resources.